It is often desirable to bias the substrate of a semiconductor device. A suitable biasing voltage level is usually outside the range provided by the power supply.
All MOS memory architectures on occasion use on-chip voltage generation. While any voltage between a ground voltage and a power supply voltage is available on a semiconductor chip, for example, a memory chip, it also possible to generate on the chip voltages that are below the ground voltage and above the power supply voltage.
The most common on-chip voltage generation in MOS memories is back-bias voltage generation (referred to as "a substrate bias voltage generation" or "a reverse-bias voltage generation"). Early MOS RAMs used a power supply voltage which provided a negative bias voltage to the substrate. On-chip back-bias generation has replaced one of these power supplies in many cases.
The most important advantage of the on-chip substrate voltage generator was the reduced probability of localized forward biasing of junctions. Such forward biasing injects electrons into the substrate leading to dynamic circuit problems and, in memory devices, for example, reduced refresh times due to a collection of electrons beneath the memory storage capacitor plate for stored ones.
Speed and power characteristics also improve when an on-chip substrate voltage generator is used because transistors operate in a flatter part of the body-effect curve and because the lower junction capacitance reduces the load. Thus, the variation of a threshold voltage caused by the body effect of a transistor is minimized and the punch-through voltage is increased.
Another advantage is that the specific bit line capacitances improve, because junction capacitances contribute more to bit line capacitance than to the total storage capacitance so that a differential signal to sense amplifiers will increase. Therefore, if a constant negative voltage is supplied to the substrate by the use of the substrate voltage generator, the performance of the memory (semiconductor) chip is improved.
FIG. 1 shows a block diagram of a conventional substrate bias voltage generator 1. The circuit includes an oscillator 10, a clock generator 12, a charge pump circuit 16 and a detector 18. The circuit pumps charge into a terminal V.sub.BB, which is connected to the substrate, and thus biases the substrate (not shown).
Thc oscillator 10 outputs an oscillation signal to Clock Generator 12. Oscillator 10 is only operational when a detected substrate voltage V.sub.BB from terminal V.sub.BB does not maintain a constant negative voltage. This is accomplished by having detector 18 apply an output to oscillator 10 by way of a feedback loop.
The clock generator 12 (or, referred to as a driver) supplies a rectangular wave signal(s) (also referred to as a clock signal(s) or a charge pump driving signal(s)) to the charge pump circuit 16 in response to the oscillation signal.
The charge pump circuit 16 is connected to substrate bias voltage terminal V.sub.BB. Circuit 16 thus performs charge pump operation in response to an output from the clock generator 12. As a result, the substrate bias voltage V.sub.BB goes to a negative voltage level.
FIG. 2 shows a prior art embodiment of the charge pump circuit of FIG. 1. Its operation is disclosed in U.S. Pat. No. 5,343,088 to Jeon. U.S. Pat. No. 5,266,842 to Park, discloses another example of the charge pump circuit 16 of FIG. 1. In addition, U.S. Pat. No. 5,120,993 to Tsay et al., discloses an example of the detector of FIG. 1. These patents are incorporated herein by reference.
Referring to FIGS. 1 and 3, driving signals CLK1 and CLK2 are transmitted from the clock generator 14 so as to be in-phase, but so as to have different pulse widths from one another. Similarly, driving signals CLK3 and CLK4 are also provided from the clock generator 14 and have the same phase but different pulse widths from one another. In addition, the phase of driving signals CLK1 and CLK2 is such that the phase is opposite from the phase of driving signals CLK3 and CLK4. A relationship between the driving signals CLK1 to CLK4 is depicted in FIG. 3 (refer to the '842 and '088 patents). As a result, the charge pump circuit 16 of FIG. 2 is capable of performing pump operations twice during a complete clock cycle.
A problem with the substrate bias voltage generator 1 of the prior art, is that the substrate bias voltage V.sub.BB isn't lowered below a value of (-Vcc+.vertline.Vtp.vertline.), wherein the symbol .vertline.Vtp.vertline. indicates an absolute value of the threshold voltage of each of the PMOS transistors 42 and 46. For example, where the power supply voltage Vcc is 5 Volts and the threshold voltage Vtp is 1 Volts, the substrate bias voltage V.sub.BB of can only be about -4 Volts. If Vcc is lowered to about 2 Volts, the substrate bias voltage generator 1 makes the substrate bias voltage V.sub.BB only about -1 Volts. Therefore, a pump efficiency of the substrate bias voltage generator 1 is decreased in proportion to the loss of the power supply voltage (an operating power supply voltage).
It is obvious to one skilled in the art that these problems are pervasive. The threshold voltage value of MOS transistor is fundamentally determined by a material forming the MOS transistor. Additionally, as the integration degree of a semiconductor memory device is increased, an operating power supply voltage used therein tends to be lowered increasingly. Even though the operating power supply voltage is reduced, the operation characteristics thereof must be maintained equally to that before the operating power supply voltage is lowered.